This invention mainly relates to an effective technique for a high-speed prefetch type DRAM (dynamic random access memory) for 3D graphics.
Semiconductor memory devices are increasingly being required to perform high-speed operations due to improvements in speed accompanying technical progress of electronic systems. Synchronous semiconductor memory devices such as SDRAM (Synchronous DRAM) are capable of performing operations in a comparatively short cycle time irrespective of the period of a sequence of operations of internal circuits.
When performing read operations or write operations on a semiconductor memory device, these operations may be speeded up by an operating parallel arrangement due to a pipeline operation of the internal circuit which forms the semiconductor memory device. On the other hand, when the semiconductor memory device is required to perform read operations and write operations alternately without a break, the problem arises that the operating speed will be largely restricted.
That is, when it is desired to perform the above alternate operations, for read-out, read data must be transferred to the external after completing internal operations of the semiconductor memory device, and write data must be transferred from the external before internal write operations are performed. Hence, when it is attempted to continuously perform internal operations for read and write, the timings of data output to the external and data input from the external overlap. When the semiconductor memory device has a common data input/output terminal, i.e., when it complies with a bi-directional bus, this overlap of data output and data input timings is not permitted.
Therefore, when the above read operation and write operation are performed alternately, it is necessary to set a latency time for internal operations so that overlap of read data transfer timing and write data transfer timing is avoided. As a result, the aforesaid operating speed or throughput is largely restricted.
In the field of 3D graphics, a high-speed semiconductor memory device is desired. In this field, images are becoming finer with one image comprising a very large number of polygons comprising a very small number of pixels, e.g., about 1 to 5. In many cases, to generate such an image, the Z buffer method is used. In the Z buffer method, a Z value which is depth data is added to each pixel on the image buffer, and compared with the Z value already written when the pixel was written. Additions are made only to pixels further in front, so only planes visible from the viewpoint of overlapping objects are generated on the image buffer.
When using the Z buffer method, before writing the first pixel, it is necessary to initialize all the Z buffers at least by xe2x80x9cthe value which represents the furthest.xe2x80x9d Otherwise, it may occur that a pixel which should actually be written cannot be written due to the wrong Z value. Also, it is necessary to fill in pixel data with xe2x80x9cthe furthest colorxe2x80x9d, i.e., a background color. As the whole screen is not necessarily covered by polygons, this is necessary to prevent pixel values which were not written when the image was generated from being indeterminate.
In a Z buffer algorithm 3D graphic system, when image data and Z data are stored in mutual addresses of the semiconductor memory device and only continuous data can be accessed, even during access such as screen refresh which does not need Z buffer data, useless Z buffer data is accessed and the effective transmission efficiency falls. This poses a problem in 3D graphic systems which require high-speed processing. The inventor thus developed a memory function for actual systems suited to this type of image generation.
From research of the literature, the Inventor found Japanese Laid-Open Published Patent Application No. 45567 of 1999 (referred to hereafter as prior art). In this prior art, in SDRAM (Synchronous DRAM), if there is a difference in the latency of a read operation and the latency of a write operation, and it is attempted to perform a write operation after a read operation, the write command cannot be input until the read data is output, and there will be a decline in the effective bandwidth of the data input/output terminal. In order to resolve the problem of bandwidth decrease, when the command immediately prior to the write command is a read command, the output signal of an intermediate data amplifier is stored in a temporary register, the read operation of a DRAM cell is suspended, the write data is input and written, the data evacuated to the temporary register after write termination is output to a data out latch, and the read operation is resumed by a clock signal. However, in this prior art, there is no mention of the bus control for actual systems oriented towards high-speed image processing according to this invention which is described hereafter.
In the above prior arts, read data which was not yet output is held by three storage means, i.e., a data amplifier, the temporary register and a data output latch, and the read data stored in the temporary register is output due to resumption of the read operation.
In this case, the input of a read command is needed for resumption of the read operation, and read data corresponding to this read command is also output after the resumed read data. Therefore, a read command must be input as a dummy command even when it is desired to output only the read data which has not yet been output, corresponding unnecessary read data will be output with a delay of plural clocks, and the bus will be occupied to output the unnecessary data.
Moreover, according to the data input/output operation of the prior art, write data will be input by the clock immediately after the read data was output. As a signal delay occurs in data transfer on the bus, in the memory circuit as shown in timing charts such as FIG. 2 and FIG. 3 of the prior art, write data is input by the clock following data output, so competition of read data and write data on the bus cannot be avoided. Hence, there is a very strong possibility that a signal error will arise due to competition between the read data and write data.
It is therefore an object of this invention to provide a semiconductor memory device which offers an improvement in speed and multi-functionality of operation.
It is another object of this invention to provide a suitable semiconductor memory device for 3D picture generation.
It is yet another object of this invention to provide a semiconductor memory device which aims at improved user-friendliness in addition to improvement in operating speed.
The above objects, other objects and new features of this invention will become clear from the description and accompany drawings of this specification.
The essential features of this invention as disclosed in this application may be simply described as follows. In a data read operation, read data is output to a data terminal in synchronism with a synchronization signal, and in a data write operation, write data is input via this data terminal in synchronism with a synchronization signal. The input of write data via the data terminal is permitted within a first time period when the output of this read data to the data terminal should be performed. Further, a second time period from when a write operation is specified to when input of write data is started, and a third time period when the input of the write data is performed, are provided, and the output of the read data to the data terminal is permitted within the second time period.
The other essential features of this invention as disclosed in this application may be simply described as follows. The semiconductor memory device comprises a bi-directional interface which performs read and write data transfer in synchronism with a clock signal, plural memory mats each forming a bank which can operate independently, and a mechanism which lowers a word line in a memory mat in which read or write is performed in a bank specified by the aforesaid read or write command after an operation according to a first read or write command, and automatically performs a sequence of operations which precharges a sense amplifier group.
When a second read or write command is issued to the same bank immediately after the above read or write command, a series of operations which begins from the start of a word line which is performed automatically, is extended until the end of the read or write command issued immediately afterwards.
The other essential features of the invention disclosed in the above application may be simply summarized as follows. The semiconductor memory device comprises a bi-directional interface which permits read and write data transfer in synchronism with a clock signal, plural memory blocks forming banks which can operate independently, a mechanism which raises a word line having an address specified by a row address in a bank specified by a bank address part in a command and reads on a sense amplifier group corresponding to the contents of plural memory cells, a mechanism which writes part or all of the bits specified by a column address part in a command from an internal data latch, and a mechanism which lowers a word line in a memory mat in which read or write is performed in a bank specified by a read or write command after the read or write command is terminated, and precharges the sense amplifier group.
The data is set to the internal data latch, a first command is performed which writes from the internal data latch to plural sense amplifier groups, a second command is performed which lowers the word line which is presently raised without precharging the sense amplifiers and then raises the specified word line, and when the second command does not follow immediately after the first or second command, ordinary operation is performed wherein the word line is lowered and the sense amplifier is precharged.
Another typical example of this invention disclosed in the present application may be simply described as follows. The semiconductor memory device in which data read operations and data write operations are specified by commands, responds to a first read command which performs data read from a memory address according to address information, and a second command which has a different command code from the first command, and which performs data read from sequential alternate memory addresses from a read start address.
Another typical example of this invention disclosed in the present application may be simply described as follows. The semiconductor memory device comprises plural memory banks, and a synchronized bi-directional interface which is common to the plural memory banks, and which performs output of read data and input of write data in synchronism with a clock signal. It permits read operation and write operation commands according to the memory bank specification. When one read operation is specified, read data is output via the synchronized bi-directional interface from the specified Fax memory bank after a first time period has elapsed, this first time period being an integral multiple of a unit time period specified by the aforesaid clock signal, from a timing at which the operation is specified. When one write operation is specified, write data is acquired by the specified memory bank via the aforesaid synchronized bi-directional interface after a second time period has elapsed, this second time period being an integral multiple of the unit time period specified by the aforesaid clock signal from a timing specified by the write operation.
The semiconductor memory device can respond to plural sequential read operation commands or plural sequential write operation commands for each unit time period specified by the aforesaid clock signal regardless of the first or second time period corresponding to the preceding operation command. When a write operation is commanded before termination of the preceding read operation, output of read data via the synchronized bi-directional interface is permitted until a second time period corresponding to a write operation command, and write data is then acquired via the synchronized bi-directional interface after the aforesaid second time period has elapsed.
Another typical example of this invention disclosed in the present application may be simply described as follows. The semiconductor memory device whereof the internal operation is specified by external operation commands, responds to a first command having a first command code, which clears the contents of plural memory cells forming a memory block in synchronism with a first unit time period determined by the synchronization signal, and a second command having a second command code different from the first command code which writes data from a data transfer region to memory cells addressed by a memory block with the second unit time period determined by the aforesaid synchronization signal as time period.